1. Field of the Invention
The present invention relates to digital signal processing, and more particularly, to a digital base booster (DBB) in a digital audio system.
2. Description of the Related Art
In general, a digital base booster (DBB) used in emphasizing a particular band of the frequency of sound reproduced in a digital audio system is implemented by a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter.
FIG. 1 illustrates the structure of an embodiment of a conventional digital base booster (DBB) implemented by an infinite impulse response (IIR) filter. Referring to FIG. 1, the conventional DBB includes three partial building blocks, including a base band filter 110, a middle band filter 130, and a treble band filter 150, as well as a first adder 170.
The base band filter 110 includes a second adder 111, a third adder 112, a first delay device 113, and first through fourth shifters 114–117.
The second adder 111 adds input data x(n) to data, in which output data qb[n−1] of the first delay device 113 is multiplied by an arbitrary coefficient −b11 stored in the first shifter 114. The third adder 112 adds data, in which the output data qb[n−1] of the first delay device 113 is multiplied by an arbitrary coefficient a11 stored in the second shifter 115, to data, in which output data qb[n] of the second adder 111 is multiplied by an arbitrary coefficient a01 stored in the third shifter 116.
The first delay device 113 delays the output of the second adder 111, and the fourth shifter 117 stores a coefficient Gb multiplied by the output of the third adder 112.
The middle band filter 130 includes a fourth adder 131, a fifth adder 132, a second delay device 133, a third delay device 134, and fifth through tenth shifters 135–140.
The fourth adder 131 adds input data x(n) and data, in which output data qm[n−1] of the second delay device 133 is multiplied by an arbitrary coefficient −b12 stored in the fifth shifter 135, to data, in which output data qm[n−2] of the third delay device 134 is multiplied by an arbitrary coefficient −b22 stored in the sixth shifter 136. The fifth adder 132 adds data, in which the output data qm[n−1] of the second delay device 133 is multiplied by an arbitrary coefficient a12 stored in the seventh shifter 137, and data, in which the output data qm[n−2] of the third delay device 134 is multiplied by an arbitrary coefficient a22 stored in the eighth shifter 138, to data, in which output data of qm[n] of the fourth adder 131 is multiplied by an arbitrary coefficient a02 stored in the ninth shifter 139. The second delay device 133 delays the output data qm[n] of the fourth adder 131, and the third delay device 134 delays the output data qm[n−1] of the second delay device 133. The tenth shifter 140 stores a coefficient Gm multiplied by the output of the fifth adder 132.
The treble band filter 150 includes a sixth adder 151, a seventh adder 152, a fourth delay device 153, and eleventh through fourteenth shifters 154–157.
The sixth adder 151 adds input data x(n) to data, in which output data qt[n−1] of the fourth delay device 153 is multiplied by an arbitrary coefficient −b13 stored in the eleventh shifter 154. The seventh adder 152 adds data, in which the output data qt[n−1] of the fourth delay device 153 is multiplied by an arbitrary coefficient a13 stored in the twelfth shifter 155, to data, in which output data qt[n] of the sixth adder 151 is multiplied by an arbitrary coefficient a03 stored in the thirteenth shifter 156. The fourth delay device 153 delays the output data qt[n] of the sixth adder 151, and the fourteenth shifter 157 stores a coefficient Gt multiplied by the output of the seventh adder 152.
The first adder 170 adds output data of the base band filter 110, the middle band filter 130, and the treble band filter 150.
A transfer function H(z) of the IIR filter of the DBB shown in FIG. 1 is as follows:
                              H          ⁡                      (            z            )                          =                              G            ⁢                                                  ⁢            b            *                                          a01                +                                  a11Z                                      -                    1                                                                              1                +                                  b11Z                                      -                    1                                                                                +                      G            ⁢                                                  ⁢            m            *                                          a02                +                                  a12Z                                      -                    1                                                  +                                  a22Z                                      -                    2                                                                              1                +                                  b12Z                                      -                    1                                                  +                                  b22Z                                      -                    2                                                                                +                      G            ⁢                                                  ⁢            t            *                                          a03                +                                  a13Z                                      -                    1                                                                              1                +                                  b13Z                                      -                    1                                                                                                          [                  Equation          ⁢                                          ⁢          1                ]            
In Equation 1, the IIR filter consists of cascade structures of a direct form.
In general, if a high-order IIR filter consists of a direct form, an arithmetic round-off error caused by an arithmetic operation in finite bits, and a coefficient quantization error occur. In particular, overflow occurs in a feedback adder, and in order to solve the problem, an IIR filter having a cascade structure consists of partial building blocks, as shown in FIG. 1.
However, in the case of the DBB system consisting of the three partial building blocks, as shown in FIG. 1, a plurality of multi-bit shifters are required to provide feedback coefficients −b11, −b12, −b22, and −b13, forward coefficients a01, a11, a02, a12, a22, a03, and a13, and gain coefficients Gb, Gm, and Gt, and for arithmetic operation of the coefficients, a multi-bit multiplier, a multi-bit feedback adder, and a forward adder are used recursively. As a result, hardware should be increased in proportion to the number of cascade structures and the size of arithmetic bits.